Electro-Static Discharge (ESD): design choices and the latest ESD protectors

READ THIS TO FIND OUT ABOUT: The three types of damage typically caused by ESD. How to identify and design-in the appropriate ESD protection.

Electro-Static Discharges (ESD) can cause damage ranging from temporary soft failures, to catastrophic failure which renders a system inoperable. Andrea Renditore, TSM, Future Electronics (Italy), outlines the design considerations for protecting systems against ESD events.

In general, there are three types of ESD damage: the first is a soft failure, where data corruption can occur to part of the data stream, or the system may latch up. This is a temporary problem and is often solved by data correction algorithms or by re-booting the system. The second is latent defects; a component within the system may be partially degraded, but is still able to function properly. A typical result of a latent defect is that the system may experience premature failure due to the defective component. The third is catastrophic failure, where a component within the system is rendered inoperable. This can manifest itself as junction breakdowns, oxide failures, or the melting of interconnects, nd it is this type of damage that the use of external ESD circuit-protection components is meant to prevent.

ESD is different from other, common over-voltage events (switching and surge transients), in that the time it takes for an ESD pulse to change from zero to maximum current and voltage is very short. The rise time of an ESD event can be less than 1ns, while other types of transient can take longer than 1µs to reach their peak. It is also worth remembering that humans can generate ESD voltages in excess of 25kV.

The trend now is to include as much ESD protection as possible at the level of the IC, to reduce the overall space and cost of adding external protection, while increasing its effectiveness. It is still important, however, to consider the use of dedicated external ESD-killer components, in conjunction with good PCB layout.

The need for board-level ESD protection will vary from system to system. The key factors that affect this decision are:

• Board layout and the ability of an ESD transient to get on to the I/O lines
• The intrinsic ESD capabilities of the ICs on the board
• The environment in which the board is intended to operate

If it is clear that supplemental ESD protection is needed, the next step is to identify the appropriate suppressor. There are several considerations to be taken into account during the selection of a suppressor, including: capacitance and signal integrity; installation; and circuit/line operating voltage.

 

 

Suppressor capacitance and signal integrity

In many situations, the inherent capacitance of a suppressor could be an advantage. Where there is a high degree of separation between the signal frequency and any unwanted frequencies, such as Electro-Magnetic Interference (EMI) and ESD transients, capacitance provides the additional benefit of filtering. Essentially acting as a low-pass filter, the suppressor provides clamping functions for transient suppression and can provide EMI filtering against unwanted, high-frequency signals which couple into the protected data line.

As an example, the headset terminals on a cell phone operate at a relatively low frequency in the audio range, while ESD and the cell phone’s operating frequency are much higher, typically 800MHz to 1,900MHz, and sometimes more. In this case, high-capacitance multi-layer varistors and/or diodes can be a good choice both for protecting against ESD from the user and for filtering radiated cell phone signals out of the headset lines.

For example, ON Semiconductor’s NUF2116MN composite device is a two-line audio EMI filter array with integrated ESD diode protection, designed for microphone/speaker applications in wireless phones, MP3 players, PDAs and so on (see Figure 1). It provides a maximum ESD protection of 30kV, compliant with IEC 61000-4-2 contact discharge, with a typical capacitance per diode of 50pF at 1MHz.

Another low data-rate example, in which the suppressor’s capacitance is not of great concern but ESD protection is very important, is represented by the automotive standard LIN2.0 bus line protection (maximum 20kBaud). NXP Semiconductor’s PESD1LIN diode suppressor, which uses an asymmetrical diode configuration to ensure optimum EMI/ESD protection to the LIN Electronic Control Unit (ECU), is suitable here.

However, the EMI filtering benefit given by high capacitance values becomes a disadvantage when the speed of the signal increases, as in multimedia applications. Examples of high-speed data lines include the HDMI 1.3 (High Definition Multimedia Interface) Hi-Speed USB2.0, IEEE 1394 and Gigabit Ethernet, which all have data rates above 100Mbits/s.

At these speeds, the capacitance that aided in the elimination of unwanted EMI noise will also begin to filter the data signals themselves. The result will be distorted data waveforms, in the form of rounded leading and trailing edges of high/low state transitions, due to the capacitance-induced slowing of rise and fall times (see Figure 2).

This will introduce timing problems, because digital circuits typically expect high and low states to be stable at specific times. As the transition time between states increases, the circuit can sense an incomplete transition, and data errors can then be introduced into the system. Thus, from a circuit protection standpoint, the goal is to provide ESD protection to the circuit while maintaining the integrity of the data.

The low impedance characteristics that are crucial for minimal distortion of high-speed signals are inherent in Tyco’s PESD family of devices. These parts are made of conductive particles dispersed into a non-conductive matrix. In normal operation, the leakage current and capacitance are very low, due to the physical gaps between the conductive particles. When the voltage of an applied ESD pulse reaches a certain trigger threshold, the gaps between each particle spark over, creating a very low resistance path.

The typical PESD capacitance is 0.20pF at 1MHz with a maximum leakage current of 10nA. The ESD capability, as per IEC 61000-4-2, is a maximum 15kV for contact discharge and 25kV for air discharge with a minimum 1k of pulse withstand (contact, level 4, 8kV ).

 

 

Suppressor installation considerations

High-speed signals and transients such as ESD bring another parasitic characteristic into play: inductance. Specifically of interest is the parasitic inductance of the board traces that are used as interconnects between the connector/s, chip/s and any support components.

As seen above with capacitance, low-frequency signals will be unaffected by the inductance that is presented by the board traces. However, as as Z_L = j2πfL, at high speeds the inductance will present an impedance component that can affect signal integrity. So, a small amount of trace inductance can translate into a substantial amount of impedance when a high-frequency signal, such as ESD, runs through it. The designer can take advantage of this phenomenon by putting as much distance as possible between the ESD suppressor and the protected chip.

There is an inverse relationship between the length of a board trace and the ESD pulse energy that finally arrives at the chip’s I/O pin. As the length of the trace increases, the strength of the ESD pulse seen at the chip decreases, which translates into reduced stress on the chip.

The ESD suppressor, therefore, should be located directly behind the connector; it should be the first board-level component that the ESD transient encounters. In addition, the ICs to be protected should be located as far away as possible.

 

Circuit/line operating voltage

This introduces some important parameters to be considered in the selection of, say, an ESD diode suppressor. This kind of device is essentially a Zener diode modified to handle large currents for very brief periods of time, while clamping at some voltage slightly over the peak operating voltage of the circuit/line to be protected. The breakdown voltage, often specified as a range, is the voltage at which the diode starts to conduct. It is measured at a test current, typically between 1mA and 10mA, and is about 10% to 15% larger than the maximum reverse working voltage, which is the maximum voltage applied to the diode with no significant current flow.

As an example, many mid-speed data lines operate at at a nominal voltage of 3.3V or 5V. In general, the corresponding I/O pins to be protected can, for very brief periods of time and depending on the IC, handle slightly more than twice the nominal value. So, in this case, we must select an ESD diode with a maximum reverse working voltage (V_rwm) greater than the maximum operating voltage, and with a maximum reverse breakdown voltage (V_brmax) less than the absolute maximum voltage rating of the pin to be protected.

ON Semiconductor’s ESD diode ESD9M5.0ST5G shows the characteristics which are required in this case: a V_rwm of 5V, V_brmax of 5.8V at an test current (It) of 1mA, and a maximum capacitance of 2.5pF, with a maximum leakage current (Ir) of 1µA at V_rwm. Its ESD capability is 10kV maximum (contact discharge, IEC 61000-4-2).

Another option here is the TransGuard® family of ESD suppressors from AVX. Their advantage is that different voltage characteristics, including the breakdown voltage, can be obtained from a single manufacturing process, thus achieving low production costs, high yields and a competitive price for the customer. The TransGuard® family’s SMD packages span 0402 to 1210, offering working voltages from 3.3V to 60V and clamping voltages from 12V to 120V.

 

Conclusion

The problem of ESD is only likely to increase, as the physical scale of integrated devices and of end products shrinks. With the right protection, however, the danger and cost implications of catastrophic equipment failure caused by ESD can be minimised, without compromising either signal integrity or power consumption.

 

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