Safe and effective power-up of high-performance microprocessors and FPGAs

by Yves Francois, Field Applications Engineer, Future Electronics (UK)

READ THIS TO FIND OUT ABOUT: Avoiding problems caused by power-on surge SMPS and linear-regulator topologies used to step-down input voltage The trade-offs between various power-up solutions

Many of today’s sophisticated digital-electronics products rely on power-hungry processors and FPGAs which require multiple power-supply rails. These complex power systems are prone to a range of faults if they are not powered-up correctly. The most important decision in the design of microprocessor and FPGA power-up circuitry is the power-architecture selection. Yves Francois, Field Applications Engineer, Future Electronics (UK) explains the various choices open to the design engineer.

The power-up sequence in FPGA and microprocessor systems is crucial because faults can cause problems both in the short term, for instance by causing the system to latch-up and abort the start-up process, or in the long term, by compromising product reliability through excessive stressing of the circuitry.

A latch-up is the inadvertent creation of a low-impedance path between the power-supply rails of an electronic component, triggering a parasitic structure which then acts as a short circuit. A latch-up condition might occur in a microprocessor if VI/O comes up before Vcore, or VI/O shuts down after Vcore ramps down. Careful sequencing of the power-on process is the only way to avoid such latch-ups.

By successfully ramping up rails sequentially, the designer can also limit the instantaneous power demand on the front-end power supply, thus reducing the risk of tripping or reaching a current-limit threshold.

 

Managing an FPGA’s power-on surge

The Power-On Surge (POS) or inrush current is the current that an FPGA draws on first applying power. POS is an inherent consequence of the architecture of today’s FPGAs. However, whilst POS cannot be eliminated, it can be managed carefully so as to avoid any damaging consequences.

An FPGA essentially consists of millions of elementary cells (complementary transistors) connected together on a die. At start-up and before initialisation has taken place, these cells are randomly in a contentious condition. This low-impedance state generates a current surge when the supply rail reaches the 0.6V to 0.8V range.

At the same time, the supply rail must also charge the inherent capacitance related to each cell, as well as charging up the decoupling (bypassing) capacitors. These capacitors typically have an aggregated capacitance value of several hundred microfarads.

The surge current, consisting of capacitance charging (I = CdV/dT) and the FPGA start-up current, can often be much greater than the steady-state current level, but the capacitance charging current can be greatly reduced if the input voltage rises at a slow rate.

The other significant variable to consider is operating temperature. For instance, the POS specified for the Spartan II device from Xilinx, a commonly-used FPGA, is 500mA at 0°C. Below 0°C the specified POS rises to 2A.

 

 

Ensuring monotonic rise and correct power sequencing

A practical way to guarantee the successful and repeatable power-up of FPGAs and microprocessors is to implement a soft-start scheme. This takes care of sequencing requirements and limits the instantaneous current drawn from the front-end power supply to an acceptable level. A typical system is shown in Figure 1.

In the vast majority of FPGA and microprocessor power-supply designs, the input voltage is larger than the core and I/O voltages require, and so must be stepped down. The most common topologies used to step down the input voltage while implementing a soft-start routine are the linear regulator and the Switch-Mode Power Supply (SMPS).

The power-loss figures, which can be calculated in a spreadsheet of the kind illustrated in Figure 2, will show the amount of power each regulator will dissipate. If the spreadsheet shows that more than a few Watts must be dissipated by a single regulator, thermal management at the board level will be a big challenge. In this circumstance, an SMPS regulator offers the best chance of minimising heat issues. Indeed, absolute power loss is more significant than efficiency. This is because it gives an indication of the intensity and number of hot spots on the board, which is directly related to the reliability of a power supply.

It is common for a power regulator to be housed in a standard package such as a TO220. Such a package will have a typical thermal resistance, junction-to-ambient (RTHja) of 60°C/W. Assuming an ambient temperature of 45°C, which is not unusual for a closed box, and a power loss of 1W, the TO220 package will reach a temperature as high as 105°C. There are no easy solutions to this. The obvious option of attaching a heat sink is expensive and is unsuited to many compact designs. It is easy to see, therefore, that thermal management is normally one of the greatest challenges facing the designer of an FPGA or microprocessor power supply.

 

 

Linear regulator or SMPS

There are two basic rules to apply in the choice of converter topology. The first rule is that, in general, the linear topology offers compelling advantages over SMPS and should be used unless overall system efficiency or thermal management is a significant problem. The second rule is that a digital power-supply rail will be relatively immune to switching noise, and is therefore better suited to an SMPS converter. By contrast, an analogue rail is highly sensitive to noise and therefore normally requires a linear regulator.

Beyond these general rules, it is possible to map out a score-card that shows the different strengths and weaknesses of linear regulators and SMPS converters.

Linear regulators offer much better frequency response and noise performance than SMPS, due to the high-frequency characteristics of the output transistors used. In addition, implementing a linear regulator in a power-supply design is straightforward, and avoids the complex decisions that are required to make best use of an SMPS.

On the other hand, linear regulators offer relatively poor efficiency, and often require external components to implement a soft-start scheme. Of course, there are different types of linear regulator, and some are better suited to FPGA and microprocessor applications than others. For instance, some applications demand a voltage rail that is less than 1V lower than an existing rail. FPGAs, for example, commonly require 2.5V and 1.8V rails. A Low Drop-Out (LDO) regulator is often suitable in this instance.

 

 

But when making the decision, the engineer must understand an important trade-off between an LDO and a standard linear regulator. Linear regulators have an output power stage based on an NPN transistor, whereas the LDO often employs a PNP transistor. This difference has profound implications for stability. Nearly all LDO regulators require the Equivalent Series Resistance (ESR) of the output capacitor to be within a specified range for stable operation. LDO manufacturers publish data that defines the boundaries of this stable region.

 

Understanding the operation of linear regulators

Linear regulators tend to provide a regulated output rail very shortly after start-up. However if the FPGA or microprocessor tries to pull more current than the linear regulator can deliver during start-up, the voltage rail will dip. This is why implementing a soft-start function when using a linear regulator requires the addition of external circuitry (see Figure 3).

Some suppliers, such as Micrel Semiconductor, offer a solution to this. The MIC68400, for example, is a high peak current LDO regulator designed specifically for powering applications that require high start-up current with lower nominal operating current, such as FPGAs, PLDs, DSPs and microcontrollers. Capable of sourcing 4A of current for start-up, the device can implement a variety of power-up and power-down protocols such as sequencing, tracking and ratiometric tracking.

 

Benefits of switching regulators

The greatest argument in favour of SMPS, for powering-up FPGAs or microprocessors, is their high efficiency and the ease of implementing a soft-start function.

Indeed, the vast majority of dedicated buck converter (step-down) SMPS come with a built-in soft-start capability implemented via a dedicated Soft-start pin. Most also have a Power-good pin, which goes High to signal when the output voltage is within the specified range.

The soft-start capability in an SMPS is enabled by a capacitor connected to the Soft-start pin. This capacitor determines the time it takes for the current source in the device to reach the maximum voltage level. The PWM signal driving the high-side switch will then gradually reach its maximum value.

These benefits, however, come at a cost. Designing with SMPS is a much more complex task than using a linear regulator. The output noise and electro-magnetic interference associated with high-speed switching operation have to be carefully managed to avoid distorting sensitive signals elsewhere on the board.

Interestingly, Micrel have released the MIC38300 which features ‘switcher plus LDO’ architecture, and offers some of the benefits of both SMPS and linear regulators. Like an LDO, it is easy to use, provides fast transient performance, a high PSRR and low noise, while delivering the efficiency of a switching regulator.

In consequence, Future Electronics would highly recommend using the SPICE simulators and IC models provided by the component manufacturers to validate a circuit design before releasing a layout for prototyping. Manufacturers including National Semiconductor, International Rectifier, Fairchild Semiconductor and Sipex make these tools freely available on their websites.

 

Conclusion

Implementing a safe power-up routine for an FPGA or microprocessor is of critical importance. The soft-start function available in most SMPS converters makes them an attractive option, and they have the added advantage of operating at high efficiency.

Many applications must, however, avoid this solution as the noise an SMPS generates will pose too great a risk to signal integrity. In this case, the designer will need to use a linear regulator which, while much more straightforward to design in than an SMPS, requires external components to implement soft-start. In addition, the designer will need to manage thermal issues very carefully in order to ensure the long-term reliability of these systems.

 

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